(1)層數:6層板HDI貫穿孔 (2)板厚:1.0mm (3)堆疊方式
a. PCB Layer define:
Layer 1 – Component Side and Ground attribute
** 除了走線外,其餘都鋪滿Ground Cooper.
** Routing (Low Speed Trace)+ Ground.
Layer 2 – Ground Layer
Layer 3 –Trace and Ground attribute.
** 除了走線外,其餘都鋪滿Ground Copper.
** Routing (High Speed Trace)+ Ground.
Layer 4 – Power Layer
** Power Panel 外層需用Ground包覆
** Power Panel至板邊的距離[Pd]必須大於Ground Panel至板邊的距離[Gd] #Pd-2mm >= Gd
Layer 5 – Ground Layer
Layer 6 – Component Side and Ground attribute
** 除了走線外,其餘都鋪滿Ground Copper.
** Routing (High Speed Trace)+ Ground.
b. BAG IC 採用Laser孔 [L1-L2, L2-L3]
c. L1-L6 貫穿孔
(4)疊層架構 (省略。。。。)
(5)Via, Trace及PAD要求與方式
(6) 高速訊號
Digital Signal Plan1 [高速訊號線優先]
優先1:DM,DP為一組differential訊號, 並於此二條訊號雙邊包覆Ground
走TOP層W = 4.5/5/4.5mil
走第3層W = 4/6/4mil
優先2:SSTX+,SSTX-為一組differential訊號, 並於此二條訊號雙邊包覆Ground
走TOP層W = 4.5/5/4.5mil
走第3層W = 4/6/4mil
優先3:SSRX+,SSRX-為一組differential訊號, 並於此二條訊號雙邊包覆Ground
走TOP層W = 4.5/5/4.5mil
走第3層W = 4/6/4mil
優先4:二線之間長度誤差+-100mil
優先5:與GROUND要求 3W
優先6: PCLK雙邊包覆Ground,高頻CLK要求 3W W = 5 mil
優先7: HSYNC, VSYNC 間距1W ,與其它TRACE間距3W W = 5 mil
優先8: DATEN_CMD, R1~R7, G0~G7及B0~B7以PCLK長度為基準,誤差+-100mil
1. Power IC週邊的Inductor & Diode接近IC端
2. ESD元件靠近Connector端
3. 高頻訊號灌孔不可超過2個
4. 高頻訊號特性阻抗參考Layer2, L3-L5, L5
5. IC每一個Power Pin皆需0.1uF下地, 並靠近IC
6. Power IC的散熱接點要與內層Ground連接
7.各個板層的Ground需用Via連接