IMAX6SL高性能处理器的pcb设计。
以下是Ddr Ram 设计的时候需要注意的地方,现以4层板设计为案例说明,阻抗,DRAM注意事项,Dram等长关系(ADDR,DATA,CLK)
1. Impendence matching
90 ohm = W:5 S:6
100 ohm = W:4 S:7
50 ohm = W:5
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2 Clock 讯号线需要以 Top 为主
如果从 CPU 需要灌孔出来就已 Bottom 层为主,Clock 灌孔处需打 2 点 GND Via
DRAM Address/Data: 50 Ohm,最多Via 两个
Clock line 请使用弧线走
3 DRam
Signals | Length | Considerations |
Address and bank | Clock length | Match the signals ± 25 mils of the value specified in the length column |
Data and buffer | Clock length | |
Control signals | Clock length | |
Clock | Lcritical (3 inches) | Match the signals of clocks signals ± 5 mils. |
DQS and DQS_B | Clock length | Match the signals of DQS signals ± 10 mils of the value specified in the length column. |