4 clock Group pulse group

Differential 4-1 DDR2 clock on, winding mode between line/space W/S=5/5 CLK+ and CLK- 1:1

Signal spacing within group suggested above 10mil (2W), group of signals at a distance of more than 15mil (3W).

The total length of 4-2 series resistance must be <900mil (22.9mm), hope to be in 1.25cm (500mil). The number of lines within each via should be the same, to less than 4 Vias.

Between 4-3 CLK+ and CLK- gap can not be larger than 20mil.

5 Control Group control group line the maximum length of 2 inches

The 5-1 control signal group DDR_CS, DDR_RAS, DDR_CAS, DDR_WE

Signal spacing within group suggested above 10mil (2W), group of signals at a distance of more than 15mil (3W).

5-2 DDR_LDM & DDR_LDQS:

From the signal using 5/9mils groups; from the non - group signal with the signal space group 5/20mils is recommended in the above 10mil (2W), group of signals at a distance of more than 15mil (3W).

5-3 total length required <900mil, hope to be in 1.25cm (500mil), Vias is less than 4.

5-4 group DQM, DQS length - error <1.5mm (60mil)

The length of the signal Xm1DATA, Xm1DQS and Xm1DQM, the 3 group, group and group, length of self error in + 1.0mm

6 Address Group address group

6-1 DDR_ADDR address line groups, using the W/S signal =5/5 space group; signal spacing within group suggested above 10mil (2W), group of signals at a distance of more than 15mil (3W).

6-2 total length required <900mil, hope to be in 1.25cm (500mil), Vias is less than 4.

7 Data Group data into 2 groups group Data

7-1 DQ[7..0] & LDM long with average length of LDQS/LDQS# when the reference + / - 60 mil, total length required <900mil, to less than 4 Vias.

As far as possible and LDQS/LDQS# using the same via number and the same layer of wire.

7-2 DQ[15..8] & UDM long with average length of UDQS/UDQS# when the reference + / - 60 mil, total length required <900mil, to less than 4 Vias.

As far as possible and UDQS/UDQS# using the same via number and the same layer of wire.

7-3 layout layer to avoid unnecessary, each DQ signal for data byte interaction swapped.

7-4 group DQ length self error <1.5mm (60mil)

7-5 Xm1DATA signal line, using the 3W principles of space, signal using a W/S =5/5 space group

7-6 Xm1DATA signal line, the same via number.

The 8 impedance value

The impedance of 8-1 Differential Trace Impedance differential line 100 ohms+/- 15%

8-2 Single-end trace Impedance impedance single-ended line 50 ohms+/- 15%

8-3 cannot be interleaved