(1) number: 6 laminates HDI perforation (2) plate thickness: 1.0mm (3) stacking

A. PCB Layer define:

Layer 1 - Component Side and Ground attribute

* * in addition to walk the line, the rest are covered with Ground Cooper.

* * Routing (Low Speed Trace) + Ground.

Layer 2 - Ground Layer

Layer 3 - Trace and Ground attribute.

* * in addition to walk the line, the rest are covered with Ground Copper.

* * Routing (High Speed Trace) + Ground.

Layer 4 - Power Layer

* * Power Panel with Ground coated layer

* * Power Panel to board edge distance [Pd] must be greater than Ground Panel to plate edge distance [Gd] #Pd-2mm > = Gd

Layer 5 - Ground Layer

Layer 6 - Component Side and Ground attribute

* * in addition to walk the line, the rest are covered with Ground Copper.

* * Routing (High Speed Trace) + Ground.

B. BAG IC uses the Laser hole [L1-L2, L2-L3]

C. L1-L6 perforation

(4) laminated structure (omitted....)

(5) Via, Trace and PAD requirements and methods

(6) high speed signal

Digital Signal Plan1 [a high speed signal line priority]

Priority 1:DM, DP is a set of differential signal, and the two signal bilateral coated Ground

TOP W = 4.5/5/4.5mil

Third layers of W = 4/6/4mil

Priority 2:SSTX+, SSTX- is a set of differential signal, and the two signal bilateral coated Ground

TOP W = 4.5/5/4.5mil

Third layers of W = 4/6/4mil

Priority 3:SSRX+, SSRX- is a set of differential signal, and the two signal bilateral coated Ground

TOP W = 4.5/5/4.5mil

Third layers of W = 4/6/4mil

Priority 4: line length between error +-100mil

5: and GROUND 3W.

Priority 6: PCLK bilateral coated Ground, frequency CLK 3W W = 5 mil

First 7: HSYNC, VSYNC spacing of 1W, and other TRACE spacing of 3W W = 5 mil

First 8: DATEN_CMD, R1~R7, G0~G7 and B0~B7 to PCLK length reference, error +-100mil

(7) the Pcb layout need to pay attention to the requirements

1 Power IC Inductor & Diode IC around the near end

2 ESD components close to the Connector terminal

3 high-frequency signal irrigation hole can not be more than 2

4 high-frequency signal characteristic impedance reference Layer2, L3-L5, L5

5 IC every Power Pin is 0.1uF, and is close to IC

Thermal contact 6 Power IC to connect with the inner Ground

7 of each plate layer of Ground with Via connection